The present invention relates to semiconductor devices, and more specifically, to vertical-type field effect transistors.
As demands to reduce the dimensions of transistor devices continue, new designs and fabrication techniques to achieve a reduced device footprint are developed. Vertical-type field effect transistors (vertical FETs) have recently been developed to achieve a reduced FET footprint without compromising the necessary FET performance. These vertical FETs are fabricated such that source/drain (S/D) regions are arranged at opposing ends of a vertical channel region, which reduces the overall device footprint.
The reduced footprint of vertical FETs makes them desirable for use in system-on-chip (SOC) applications, which provide increased component density and integration of numerous functions onto a single silicon chip. One such example of a SOC application is the implementation of antifuses to form on-chip one-time programmable (OTP) memory cells.